The invention relates generally to the field of electronic and microelectronic packaging, and in particular how to connecting multiple substrates, chips or die to each other through a half-conductive layer forming a resistive network. Methods for power transport and signal communication through the half-conductive layer, methods for making and application of the half-conductive layer, and methods for testing and repairing such systems are contemplated.
Prior methods for connecting two substrates involved the use of conductive, metallic interconnections such a solder bumps between mating electrodes on the substrates. Before connection, solder or a complex metallurgical mix of metals is deposited on the electrodes by plating or by screen-printing. The substrates are then aligned such that mating electrodes and their associated solder bumps are in contact, followed by heating and compression. The solder melts and makes a galvanic contact. A disadvantage is that the resulting metallic interconnection is brittle. Temperature cycling induces cycled strain which may induce microscopic cracks and defects in the brittle solder bumps to grow. Eventually one large crack may expand across the whole solder-bump area, and the electrical connection between the mating electrodes is broken. Additionally, moisture and corrosion can also contribute to the growth of micro-cracks and to resulting undesired open circuits between mating electrodes. The yield and reliability of solder-bump interconnection is degraded by these phenomena.
An additional disadvantage of prior art solder bump interconnects is the limited number of channels (between mating electrodes) per square centimeter, since the solder islands require adequate spacing. Furthermore, several extra lithography steps are required on both mating substrates to form the solder bumps, making the system more costly. The low reworkability and low detachability is a bad property at system assembly time. Because it is difficult if not at times impossible to detach chips interconnected using solder bump technology, the failure of one of a set of chips may render the total system valueless. As a result chips need to be tested thoroughly before connection with solder bump technology. As chips become more complex and exhaustive testing becomes more difficult or nearly impossible, detachability becomes even more important. Moreover the solder-bump process is a dirty process with solvents and solder-flux. Processed parts require cleaning, and the use is restricted to high-temperature substrates.
Many of the problems linked to the metallurgy of the solder are solved using conductive polymer bumps. The conductive polymer bump technology however requires that the conducting polymer bumps are isolated completely from each other, to avoid short-circuiting. This limits the number of channels per square centimeter and requires precise lithography or screen-printing ability, thus increasing the cost and size of the interconnection. Additionally, at the moment of connection, the pressure (in grams/pad) has to be controlled carefully, not to squash the bumps flat, which in turn creates shorts. The bump formation process limits the material choice. Bumps require precise height. To obtain a solid construction, an under-filling material is required. The layer connecting the two substrates with conductive polymer and under filling material is macroscopically inhomogeneous, creating stress on the conductive polymer bumps and the underlying substrate. It is advisable, therefore, not to put circuitry below the conductive polymer bumps.
A homogeneous layer can connect opposing metallic pads through capacitive coupling. Systems are known in which one plate of a capacitance is formed on a first substrate and the other plate is formed on a second substrate. The resulting coupling capacitance is then used as a feed-through capacitance for signals and ac power. Such a system allows in principle a high number of interconnects, or channels, per square centimeter. The interconnect layer must have a high dielectric factor, which limits the number of usable materials. To obtain sufficient coupling the thickness of the interconnect layer should be very thin. To transmit signals through the capacitive interconnect layer, the signal edges have to be very steep for the signal to get transmitted since the low frequency part of a signal is filtered out. As a consequence, dc power cannot be transmitted through capacitive coupling.
Connection of a chip to a multi-chip module (MCM) substrate or a printed circuit board (PCB) involves additional wiring on the MCM or PCB, which wiring is typically several pF/cm, much more capacitive then the interconnect feed-through capacitance and forms a voltage divider therewith. As a result, only a small fraction of the transmitted signal voltage passes to the receiving detector, diminishing the voltage swing of the received voltage to unacceptable levels. A solution to this disadvantage requires the use of transmission lines with integrated termination resistors, and permanent dissipating receivers. Another attempt to work without a patterned layer and to avoid associated lithography costs, is the use of an anisotropic conductive adhesive. The adhesive base material contains metal particles of a certain diameter (e.g. 10-micron). When the substrates are brought in alignment, the distance between mating metal pads on the substrates is expected to be a little thinner than the diameter of the conducting particles. In this way, the conducting particles get compressed, forming a galvanic connection path between the mating pads. In the lateral direction, the particles do not touch each other, avoiding electrical connection between neighboring pads. In other words, in the direction normal to the layer there is conductivity; in lateral directions, there is electrical insulation. The disadvantage with that solution is that spacing between the mating pads has to be carefully controlled. Stresses resulting from compressing the conductive particles in the connection layer will concentrate locally, i.e. at the contact interface between the conductive particle and the metal pad. This force may damage any circuitry on the substrate below the metal pad. The thickness of the layer in between metal pads needs to be smaller than between insulation regions. When connecting CMOS chips, this will require extra plating for the metal pads to reach higher than the surrounding capping layer. Furthermore, the interconnect-pitch is determined by the statistics of the metal particles. For reliability reasons, at least a few particles should share the connection current. Hence, the metal pads must be of sufficient geometry to contact several conductive particles, thus increasing the size of the pads.
The invention provides for a system or circuit comprising electronic components. A first electronic component has a plurality of electrical contact pads and a second electronic component also has a plurality of electrical contact pads. At least one of the plurality of electrical pads on the first component is substantially aligned with one of the plurality of contact pads on the second component. An isotropically conductive layer between the first and second components couples the first and second plurality of contact pads. Alternatively, two separate unpatterned conductive layers may be employed, the layers being of essentially equal thickness and adjacent one another, but electrically isolated from one another. One layer electrically connects a first plurality of contact pads on the first component to a first plurality of contact pads on the second component, and the second layer couples a second plurality of contact pads on the first component to a second plurality of contact pads on the second component.